US 12,482,518 B2
Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read current
Kedar Janardan Dhori, Ghaziabad (IN); Nitin Chawla, Noida (IN); Promod Kumar, Greater Noida (IN); Harsh Rawat, Faridabad (IN); and Manuj Ayodhyawasi, Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Apr. 20, 2023, as Appl. No. 18/137,159.
Claims priority of provisional application 63/345,558, filed on May 25, 2022.
Prior Publication US 2023/0386564 A1, Nov. 30, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); G11C 11/419 (2006.01); G11C 11/54 (2006.01); G06N 3/065 (2023.01)
CPC G11C 11/4096 (2013.01) [G11C 7/1006 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/419 (2013.01); G11C 11/54 (2013.01); G06N 3/065 (2023.01)] 12 Claims
OG exemplary drawing
 
1. An in-memory computation circuit, comprising:
a memory array including a plurality of memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a first bit line and second bit line connected to the memory cells of the column;
a word line driver circuit for each row having an output connected to drive the word line of the row;
a row controller circuit configured to simultaneously actuate the plurality of word lines by applying pulses through the word line driver circuits to the word lines in response to feature data for an in-memory compute operation; and
a column processing circuit including a read circuit coupled to the first and second bit lines, wherein each read circuit comprises:
a first sensing circuit comprising a first analog-to-digital converter circuit configured to convert a first bit line signal generated on the first bit line in response to the in-memory compute operation and generate a first digital signal;
a second sensing circuit comprising a second analog-to-digital converter circuit configured to convert a second bit line signal generated on the second bit line in response to the in-memory compute operation and generate a second digital signal; and
a digital signal processing circuit configured to average the first and second digital signals to generate an output signal indicative of a result of the in-memory compute operation.