| CPC G11C 11/4085 (2013.01) [G11C 11/2257 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1441 (2013.01)] | 25 Claims |

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1. An apparatus comprising:
a first semiconductor die comprising a plurality of word line conductors, each word line conductor of the plurality of word line conductors operable to access a respective set of one or more memory cells of the first semiconductor die;
a second semiconductor die comprising a plurality of word line driver circuits, wherein the plurality of word line driver circuits are operable based at least in part on one or more doped portions of a crystalline semiconductor substrate of the second semiconductor die; and
a plurality of electrical contacts, each electrical contact of the plurality of electrical contacts extending through at least a portion of the second semiconductor die and coupling a respective word line conductor of the plurality of word line conductors with a respective word line driver circuit of the plurality of word line driver circuits, wherein each electrical contact of the plurality of electrical contacts extends through the crystalline semiconductor substrate of the second semiconductor die.
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