US 12,482,511 B2
Techniques for memory cell reset using dummy word lines
Yuan He, Boise, ID (US); and Wenlun Zhang, Tokyo (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 2, 2023, as Appl. No. 18/310,715.
Claims priority of provisional application 63/347,838, filed on Jun. 1, 2022.
Prior Publication US 2023/0395123 A1, Dec. 7, 2023
Int. Cl. G11C 11/4072 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4072 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first bit line;
a first transistor coupled between the first bit line and a first capacitive memory element;
a second transistor coupled between the first bit line and a voltage node supplied with a first voltage for a reset operation;
a first word line coupled with a first control gate of the first transistor;
a second word line coupled with a second control gate of the second transistor; and
a controller, for the reset operation, configured to:
activate the second word line to supply the first voltage to the first bit line through the second transistor; and
activate the first word line to supply the first voltage, which has been supplied to the first bit line, to the first capacitive memory element such that the first capacitive memory element is reset.