US 12,482,505 B2
Page buffer circuit and operating method thereof adapted for page read device
Bo-Rong Lin, Taichung (TW); Han-Wen Hu, Zhubei (TW); Yung-Chun Li, New Taipei (TW); and Huai-Mu Wang, New Taipei (TW)
Assigned to MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed by MACRONIX INTERNATIONAL CO., LTD., Hsinchu (TW)
Filed on Dec. 11, 2023, as Appl. No. 18/534,840.
Prior Publication US 2025/0191621 A1, Jun. 12, 2025
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01)
CPC G11C 7/1039 (2013.01) [G11C 7/1087 (2013.01); G11C 7/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A page buffer circuit adapted for a page-read device, wherein the page read device includes a memory array having a plurality of pages and a plurality of bit lines, the page buffer circuit comprising:
a plurality of first latches, for receiving a weight-vector from a corresponding one of the pages through the bit lines, and importing an input-vector through a data input/output path, wherein the weight-vector has a plurality of weight bit-data, and the input-vector has a plurality of input bit-data;
a plurality of second latches, for storing the plurality input bit-data of the input-vector;
a plurality of logic operation units, coupled to the plurality first latches to receive the plurality weight bit-data, and coupled to the plurality second latches to receive the plurality input bit-data, each of the logic operation units is used to perform a logic operation of a corresponding one of the plurality input bit-data and a corresponding one of the plurality weight bit-data to generate a logic operation result, and the logic operation result is sent to one of the plurality first latches; and
a control circuit, for selectively enabling the logic operation units to perform the logic operation.