US 12,482,504 B2
Page buffer circuit and operation method thereof
Soo Yeol Chai, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Oct. 26, 2022, as Appl. No. 17/973,988.
Claims priority of application No. 10-2022-0034787 (KR), filed on Mar. 21, 2022.
Prior Publication US 2023/0298637 A1, Sep. 21, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01)
CPC G11C 7/1039 (2013.01) [G11C 7/1069 (2013.01); G11C 7/12 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A page buffer circuit comprising:
a data transfer circuit configured to transfer data, received through a bit line, to a first sensing node and to a second sensing node during a data sensing operation;
a first latch circuit configured to sense the data transferred to the first sensing node, and store the sensed data transferred to the first sensing node; and
a second latch circuit configured to sense the data transferred to the second sensing node, and store the sensed data transferred to the second sensing node,
wherein the first latch circuit comprises:
a latch driving circuit coupled to the second sensing node and configured to store the data transferred to the first sensing node in a data node and discharge the second sensing node based on the data node; and
a current control circuit coupled to the data node and the first sensing node and configured to control a driving current of the data node on the basis of the data transferred to the first sensing node.