| CPC G09G 3/3266 (2013.01) [G09G 3/32 (2013.01); G09G 3/3291 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0291 (2013.01)] | 14 Claims |
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1. A display panel, comprising:
a display area where a plurality of subpixels are disposed;
a gate driving circuit disposed in a non-display area outside the display area to supply a plurality of scan signals to the plurality of subpixels, and including a plurality of gate driving panel circuits configured to generate at least one scan signal;
a plurality of gate high-potential voltage lines which are disposed in a first side of the gate driving circuit for transferring a plurality of gate high-potential voltages;
a plurality of gate low-potential voltage lines which are disposed in a second side of the gate driving circuit for transferring a plurality of gate low-potential voltages; and
a plurality of gate low-potential voltage connection lines which extend through a central area of the gate driving circuit for transferring the plurality of gate low-potential voltages to the gate driving circuit,
wherein the plurality of gate driving panel circuits include:
an output buffer block configured to output the at least one scan signal based on voltage states of a first node and a second node;
a logic block configured to control voltages of the first node and the second node; and
a real-time sensing control block configured to control the logic block to perform a real-time sensing driving operation.
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