US 12,482,424 B2
Display device
Peng Zhang, Guangdong (CN); and Yuanjun Hsu, Guangdong (CN)
Assigned to Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Shenzhen (CN)
Appl. No. 17/298,633
Filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Guangdong (CN)
PCT Filed May 10, 2021, PCT No. PCT/CN2021/092717
§ 371(c)(1), (2) Date Oct. 27, 2022,
PCT Pub. No. WO2022/222204, PCT Pub. Date Oct. 27, 2022.
Claims priority of application No. 202110463324.9 (CN), filed on Apr. 23, 2021.
Prior Publication US 2024/0013727 A1, Jan. 11, 2024
Int. Cl. G09G 3/3266 (2016.01); H10K 59/121 (2023.01); H10K 59/126 (2023.01); H10K 59/131 (2023.01)
CPC G09G 3/3266 (2013.01) [H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/126 (2023.02); H10K 59/131 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A display device, comprising a display area and a non-display area surrounding a periphery of the display area, wherein the non-display area is provided with a gate driving area, the gate driving area comprises a gate driving circuit configured to drive the display area, the gate driving circuit comprises an output pull-up module, the output pull-up module comprises a first transistor device, and the first transistor device comprises:
a first metal layer;
a buffer layer disposed on the first metal layer;
an active layer disposed on the buffer layer and corresponding to the first metal layer;
a gate insulating layer disposed on the active layer;
a gate layer disposed on the gate insulating layer and corresponding to the active layer;
an interlayer insulating layer disposed on the buffer layer and completely covering the gate layer; and
a second metal layer disposed on the interlayer insulating layer, wherein the second metal layer comprises a source electrode, a drain electrode, a first signal wire, and a second signal wire; the source electrode is electrically connected to an end of the active layer, the drain electrode is electrically connected to another end of the active layer, the first signal wire is electrically connected to the gate layer to form a top-gate structure and is configured to input a first gate signal, and the second signal wire is electrically connected to the first metal layer to form a bottom-gate structure and is configured to input a second gate signal;
wherein the gate driving area comprises a first capacitor electrode plate, the first capacitor electrode plate and the first metal layer are disposed on a same layer, the second metal layer comprises a second capacitor electrode plate, the active layer comprises a third capacitor electrode plate, the first capacitor electrode plate is electrically connected to the second capacitor electrode plate, and the third capacitor electrode plate is correspondingly disposed between the first capacitor electrode plate and the second capacitor electrode plate to form a capacitor.