US 12,482,400 B2
Shift register unit, gate driving circuit, and display apparatus
Peng Jiang, Beijing (CN); Xiaoxiao Chen, Beijing (CN); Yun Li, Beijing (CN); Ning Zhu, Beijing (CN); and Jiantao Liu, Beijing (CN)
Assigned to Wuhan BOE Optoelectronics Technology Co., Ltd., Hubei (CN); and Beijing BOE Technology Development Co., Ltd., Beijing (CN)
Appl. No. 18/691,778
Filed by Wuhan BOE Optoelectronics Technology Co., Ltd., Hubei (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Sep. 21, 2022, PCT No. PCT/CN2022/120228
§ 371(c)(1), (2) Date Mar. 13, 2024,
PCT Pub. No. WO2023/071633, PCT Pub. Date May 4, 2023.
Claims priority of application No. 202111245661.7 (CN), filed on Oct. 26, 2021.
Prior Publication US 2024/0321172 A1, Sep. 26, 2024
Int. Cl. G09G 3/20 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/2092 (2013.01) [G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G11C 19/287 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A shift register unit, comprising:
an input circuit configured to provide a signal from a second input signal terminal to a first node in response to a signal from a first input signal terminal;
a reset circuit configured to provide a signal from a first reference signal terminal to the first node in response to a signal from a reset signal terminal;
a node control circuit configured to at least adjust a level of a signal at the first node according to a signal from a second reference signal terminal and a signal from a third reference signal terminal;
a cascade output circuit configured to provide a signal from a clock signal terminal to a cascade output terminal in response to the signal at the first node; and
a driving output circuit configured to provide the signal from the clock signal terminal to a driving output terminal in response to the signal at the first node;
wherein the node control circuit comprises: a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; wherein
a gate and a first electrode of the fourth transistor are both electrically connected with the third reference signal terminal, and a second electrode of the fourth transistor is electrically connected with a gate of the fifth transistor;
a first electrode of the fifth transistor is electrically connected with the third reference signal terminal, and a second electrode of the fifth transistor is electrically connected with a second node;
a gate of the sixth transistor is electrically connected with the first node, a first electrode of the sixth transistor is electrically connected with the second reference signal terminal, and a second electrode of the sixth transistor is electrically connected with the second node; and
a gate of the seventh transistor is electrically connected with the second node, a first electrode of the seventh transistor is electrically connected with the second reference signal terminal, and a second electrode of the seventh transistor is electrically connected with the first node.