US 12,481,905 B2
Synthesis of quantum circuits from native gates
Eric Peterson, Yorktown Heights, NY (US); Lev Samuel Bishop, Dobbs Ferry, NY (US); and Ali Javadiabhari, Sleepy Hollow, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jun. 22, 2022, as Appl. No. 17/847,014.
Claims priority of provisional application 63/271,212, filed on Oct. 24, 2021.
Prior Publication US 2023/0289638 A1, Sep. 14, 2023
Int. Cl. G06F 17/00 (2019.01); G06N 10/20 (2022.01); G06N 10/80 (2022.01)
CPC G06N 10/20 (2022.01) [G06N 10/80 (2022.01)] 20 Claims
OG exemplary drawing
 
1. A method for synthesizing a quantum circuit for use on a quantum computational device, comprising:
receiving, on a classical computer, information for a target operation to be implemented on said quantum computational device;
receiving, on said classical computer, information regarding native qubit gates that are available on said quantum computational device to be used to implement said quantum circuit;
determining, on said classical computer, each of a plurality of quantum circuits formed from said native qubit gates such that each of said plurality of quantum circuits will perform a function substantially equivalent to said target operation when implemented on the quantum computational device;
selecting, on said classical computer, one of said plurality of quantum circuits formed from said native qubit gates based on a performance criterion of said quantum computational device,
wherein said target operation is a unitary operator comprising one-qubit and two-qubit operations,
wherein said native qubit gates are one-qubit and XX-type gates, and
wherein said performance criterion is based on operating parameters of said quantum computational device.