US 12,481,867 B2
Memory for artificial neural network accelerator
Teyuh Alice Chou, Ann Arbor, MI (US); Mudit Bhargava, Austin, TX (US); Supreet Jeloka, Austin, TX (US); Fernando Garcia Redondo, Cambridge (GB); and Paul Nicholas Whatmough, Cambridge, MA (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Apr. 28, 2021, as Appl. No. 17/242,721.
Prior Publication US 2022/0351032 A1, Nov. 3, 2022
Int. Cl. G06N 3/065 (2023.01); G06F 17/16 (2006.01); G11C 5/02 (2006.01); G11C 7/10 (2006.01); G11C 7/16 (2006.01)
CPC G06N 3/065 (2023.01) [G06F 17/16 (2013.01); G11C 5/02 (2013.01); G11C 7/1006 (2013.01); G11C 7/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A compute-in-memory (CIM) array module for an artificial neural network (ANN) accelerator, comprising:
a CIM array including a plurality of row signal lines, a plurality of column signal lines, and a plurality of cells, each cell located at an intersection of a row signal line and a column signal line, each cell having a conductance that is programmable between a minimum conductance value and a maximum conductance value;
a plurality of digital-to-analog converters (DACs), each DAC configured to receive an input data value, convert the input data value to a voltage level, and apply the voltage level to a respective row signal line;
a plurality of analog-to-digital converters (ADCs), each ADC configured to receive a sampled signal via a sampled signal line, and generate an output data value based on the sampled signal;
a plurality of saturation detection units (SDUs), each SDU including a capacitor and a comparator, the capacitor selectively coupled to a respective column signal line and a respective sampled signal line, the comparator selectively coupled to the respective column signal line and coupled to a reference voltage signal line and a saturation signal line, each SDU configured to:
generate an analog signal based on the voltage levels applied to the row signal lines and the conductances of the cells of the respective column signal line,
generate a respective sampled signal based on the analog signal,
transmit the respective sampled signal, via the sampled signal line, to a respective ADC,
receive a reference voltage signal from the reference voltage signal line, the reference voltage signal having a voltage level that indicates a saturation threshold,
determine whether a voltage level of the sampled signal is greater than the voltage level of the reference voltage signal, and
transmit a saturation signal, via the respective saturation signal line, when the voltage level of the sampled signal is greater than the voltage level of the reference voltage signal; and
a controller, coupled to the SDUs, configured to receive the saturation signals.