US 12,481,813 B2
Test point insertion in analog circuit design testing
Mayukh Bhattacharya, Palo Alto, CA (US); and Peilin Jiang, SAnta Clara, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Jan. 9, 2023, as Appl. No. 18/094,951.
Prior Publication US 2024/0232485 A1, Jul. 11, 2024
Int. Cl. G06F 30/3308 (2020.01); G06F 30/20 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 11/00 (2006.01); G06F 11/26 (2006.01)
CPC G06F 30/3308 (2020.01) [G06F 11/008 (2013.01); G06F 11/261 (2013.01); G06F 30/20 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method for generating a circuit design test, the method comprising:
partitioning a circuit design into a plurality of blocks;
determining a first potential defect and a second potential defect for the circuit design;
simulating the circuit design by injecting, into the circuit design, the first potential defect to produce a first set of outputs of the plurality of blocks;
simulating the circuit design by injecting, into the circuit design, the second potential defect to produce a second set of outputs of the plurality of blocks;
determining, by a processor and based at least in part on the first set of outputs of the plurality of blocks and the second set of outputs of the plurality of blocks, a set of output nodes of the plurality of blocks; and
generating a test that, when executed, measures signals at the set of output nodes.