US 12,481,811 B1
Circuit design modification based on timing tradeoff
Jordan Moxon, Mountain View, CA (US); Kwangsoo Han, Austin, TX (US); and Zi Wang, Dallas, TX (US)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Dec. 5, 2022, as Appl. No. 18/075,109.
Int. Cl. G06F 30/327 (2020.01); G06F 30/3312 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 30/3312 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory computer-readable medium comprising instructions that, when executed by a hardware processor of a device, cause the device to perform operations comprising:
accessing data that describes a netlist for a circuit design;
determining a select region of the circuit design for a transformation configured to alter a logic of the select region, the select region corresponding to a subset of the netlist;
determining, from a class of transforms, a set of transforms for the select region; and
for an individual transform in the set of transforms:
determining, based on a timing-aware tradeoff model, whether application of the individual transform on the select region is acceptable, the timing-aware tradeoff model being configured to evaluate transforms based on a constrained timing arc of the select region; and
in response to determining that the application of the individual transform on the region is acceptable, committing the individual transform to the select region to generate an altered region that replaces the select region in the circuit design.