| CPC G06F 21/602 (2013.01) [G06F 21/78 (2013.01)] | 20 Claims |

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1. A memory controller comprising:
a first interface configured to perform data communication with a first external device comprising a host memory buffer being a portion of a volatile memory provided in the first external device;
a second interface configured to generate signal for controlling an operation of a second external device and transmit the signal; and
a processor configured to:
receive keys from the first external device,
encrypt the keys by an encryption key of the memory controller,
store the encrypted keys in a key area provided in the host memory buffer,
receive, from the first external device, a data write command to write data to the second external device,
read one of the encrypted keys stored in the key area,
encrypt, in response to the data write command, the data by using the read key, and
control the encrypted data to be written to the second external device.
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