US 12,481,618 B2
Context load mechanism in a coarse-grained reconfigurable array processor
Bryan Hornung, Plano, TX (US); Douglas Vanesko, Dallas, TX (US); and David Patrick, McKinney, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 14, 2024, as Appl. No. 18/743,637.
Application 18/743,637 is a continuation of application No. 17/899,714, filed on Aug. 31, 2022, granted, now 12,038,868.
Prior Publication US 2024/0330237 A1, Oct. 3, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 15/80 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 15/78 (2006.01)
CPC G06F 15/80 (2013.01) [G06F 9/30018 (2013.01); G06F 15/7867 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A context load circuitry configured to communicate with a memory, the context load circuitry operable to load context state data for a coarse-grained reconfigurable array processor, the context load circuitry configured to:
determine a context mask address from a context mask base address and a kernel identifier, the context mask base address stored in a first registry, the context mask base address for a context mask region in the memory;
determine a context state address from a context state base address and the kernel identifier, the context state base address for a context state region in the memory, and the context state base address stored in a second registry;
use a context mask at the context mask address to determine a corresponding active context state; and
load the corresponding active context state into the coarse-grained reconfigurable array processor.