US 12,481,609 B2
FIFO data buffer with multi-load
Amiram Hochman, Raanana (IL)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Appl. No. 18/729,643
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
PCT Filed Dec. 27, 2022, PCT No. PCT/US2022/082397
§ 371(c)(1), (2) Date Jul. 17, 2024,
PCT Pub. No. WO2023/146721, PCT Pub. Date Aug. 3, 2023.
Claims priority of application No. 2030739 (NL), filed on Jan. 27, 2022.
Prior Publication US 2025/0094368 A1, Mar. 20, 2025
Int. Cl. G06F 13/20 (2006.01); G06F 1/04 (2006.01)
CPC G06F 13/20 (2013.01) [G06F 1/04 (2013.01); G06F 2213/40 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a first in first out, FIFO data buffer comprising
a load shift register comprising a plurality of register locations, the load shift register being configured to shift data between at least two register locations of the plurality of register locations controllable on at least one shift instruction, and to load data into at least one of the plurality of register locations controllable on at least one load instruction,
a request line encoder configured to receive one or more requests each comprising a corresponding priority value, and to determine a request number value based at least in part on the one or more requests received, one or more requests currently loaded in the load shift register, and a state, the request number value representing a number of the one or more requests received to load into the load shift register, and
a state machine configured to determine, based at least in part on the request number value, the state, one or more shift instructions, and one or more load instructions; and
one or more clocks to provide a clock signal to the load shift register, the request line encoder, and the state machine.