US 12,481,597 B2
Memory processing system of enhanced efficiency and method thereof
En-Shou Tang, Hsinchu (TW); Yuan-Chun Lin, Hsinchu (TW); Kai-Hsiang Chang, Hsinchu (TW); and Yi-Che Tsai, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsin-Chu (TW)
Filed on Aug. 18, 2023, as Appl. No. 18/235,365.
Claims priority of provisional application 63/446,309, filed on Feb. 16, 2023.
Prior Publication US 2024/0281382 A1, Aug. 22, 2024
Int. Cl. G06F 12/1009 (2016.01); G06F 12/1027 (2016.01); G06F 13/16 (2006.01)
CPC G06F 12/1009 (2013.01) [G06F 12/1027 (2013.01); G06F 13/1689 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory processing system comprising:
a processor configured to generate a plurality of virtual addresses, each virtual address of the plurality of virtual addresses comprising a base address and an offset;
a main memory comprising:
a plurality of data corresponding to a plurality of physical addresses, each physical address of the plurality of physical addresses comprising a base address and an offset; and
a main page table configured to map the plurality of virtual addresses to the plurality of physical addresses;
a memory management unit (MMU) coupled to the processor and the main memory, comprising:
a translation lookaside buffer (TLB) coupled to the processor and the main memory, configured to store a first page table mapping a first set of base addresses of virtual addresses to a first set of base addresses of physical addresses, and to perform address translation;
a table walk unit coupled to the translation lookaside buffer and the main memory, configured to access the plurality of physical addresses in the main memory, and to store a second page table mapping a second set of base addresses of virtual addresses to a second set of base addresses of physical addresses;
a merger coupled to the translation lookaside buffer and the processor, configured to merge memory transactions;
wherein the TLB performs address translation by retrieving a physical address according to a virtual address from the first page table in the TLB, the second page table in the table walk unit or the main page table in the main memory; and
the merger merges a plurality of memory transactions having consecutive offsets with an identical base address within a merge window into a single memory transaction.