US 12,481,591 B2
Prediction confirmation for cache subsystem
Ronald P. Hall, Cedar Park, TX (US); Mary D. Brown, Austin, TX (US); Balaji Kadambi, Austin, TX (US); and Mahesh K. Reddy, Austin, TX (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 9, 2024, as Appl. No. 18/438,111.
Application 18/438,111 is a continuation of application No. PCT/US2022/037708, filed on Jul. 20, 2022.
Application PCT/US2022/037708 is a continuation of application No. 17/397,429, filed on Aug. 9, 2021, granted, now 11,487,667, issued on Nov. 1, 2022.
Prior Publication US 2024/0176744 A1, May 30, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 12/0862 (2016.01)
CPC G06F 12/0862 (2013.01) [G06F 2212/6032 (2013.04)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a prediction circuit configured to, in response to a cache access request, generate a prediction of a particular one of a plurality of ways in a cache memory includes a particular cache line associated with the cache access request;
a comparison circuit configured to determine if the prediction is correct, wherein, to determine if the prediction is correct, the comparison circuit is configured to compare a first tag associated with the particular cache line and a second tag associated with the particular one of the plurality of ways; and
a confirmation bit memory, wherein the prediction circuit is configured to, in response to the comparison circuit determining that the prediction was correct, set a confirmation bit in the confirmation bit memory;
wherein, for a subsequent cache access request to the particular cache line, the comparison circuit is configured to, in response to determining that the confirmation bit is set in the confirmation bit memory, forego performing a comparison of the first tag and the second tag.