US 12,481,577 B2
Instruction stream retrograding to enhance random test generation
Bryan G. Hickerson, Cedar Park, TX (US); Craig Atherton, Burlington, VT (US); Michal Rimon, Nofit (IL); Avishai Moshe Fedida, Gesher Ha'Ziv (IL); and Ofer Peled, Haifa (IL)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 16, 2023, as Appl. No. 18/450,615.
Prior Publication US 2025/0061050 A1, Feb. 20, 2025
Int. Cl. G06F 11/36 (2025.01); G06F 9/30 (2018.01); G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 11/3668 (2025.01); G06F 11/263 (2006.01)
CPC G06F 11/3688 (2013.01) [G06F 9/3005 (2013.01); G06F 11/3684 (2013.01); G06F 9/462 (2013.01); G06F 9/4881 (2013.01); G06F 11/263 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer system for retrograding an instruction stream to enhance random test generation comprising:
a random test generation system comprising a processor and configured to:
generate a test case for a design-under-test (DUT) comprising:
position one or more placeholder instructions in the test case;
identify one or more benefiting instructions; and
generate one or more load instructions configured to identify one or more respective memory addresses that are to be accessed through one or more respective retrograding instructions; and
execute the test case, by replacing the one or more placeholder instructions into the one or more respective retrograding instructions, wherein the one or more retrograding instructions influence the one or more benefiting instructions.