US 12,481,554 B2
EEPROM emulation method
Jawad Benhammadi, Pont de Claix (FR)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Feb. 1, 2024, as Appl. No. 18/430,259.
Claims priority of application No. FR2301000 (FR), filed on Feb. 2, 2023.
Prior Publication US 2024/0264905 A1, Aug. 8, 2024
Int. Cl. G06F 11/10 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/1044 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A method of electrically-erasable programmable read-only memory (EEPROM) emulation in a phase-change memory of a circuit integrating a microprocessor, wherein the phase-change memory includes a data zone and an error correction zone, the method comprising the following steps:
defining a granularity for writing into lines of the data zone of the phase-change memory according to a size of each data packet to be written;
deactivating the error correction zone during EEPROM emulation;
associating with each data packet a first error correction code calculated by a program executed by said microprocessor; and
storing a plurality of data packets and their associated first error correction codes in a same line of the data zone of the phase-change memory.