US 12,481,553 B2
System, method and apparatus for reducing power consumption of error correction coding using compacted data blocks
Qiuxu Zhuo, Shanghai (CN); Karthik Ananthanarayanan, Milpitas, CA (US); Hsing-Min Chen, Santa Clara, CA (US); John Holm, Beaverton, OR (US); and Anthony Luck, San Jose, CA (US)
Assigned to Intel Corportation, Santa Clara, CA (US)
Appl. No. 18/572,226
Filed by INTEL CORPORATION, Santa Clara, CA (US)
PCT Filed Dec. 17, 2021, PCT No. PCT/CN2021/139082
§ 371(c)(1), (2) Date Dec. 20, 2023,
PCT Pub. No. WO2023/108600, PCT Pub. Date Jun. 22, 2023.
Prior Publication US 2024/0289213 A1, Aug. 29, 2024
Int. Cl. G06F 11/10 (2006.01)
CPC G06F 11/1048 (2013.01) 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first circuit to compact a plurality of data blocks to a compacted data block and to compact a plurality of error correction codes (ECCs) associated with the plurality of data blocks to a compacted ECC; and
a second circuit to generate a generated ECC for the compacted data block, wherein the apparatus is to directly send the plurality of data blocks to a destination circuit without error detection on the plurality of data blocks based at least in part on the compacted ECC and the generated ECC.