US 12,481,550 B2
Device and methods for managing the data integrity of read and write operations
Peng Xu, Los Angeles, CA (US); Fei Liu, Los Angeles, CA (US); Kyoungryun Bae, Los Angeles, CA (US); Hao Wang, Los Angeles, CA (US); Ming Lin, Los Angeles, CA (US); Wei Tang, Los Angeles, CA (US); Sheng Qiu, Los Angeles, CA (US); and Yang Liu, Los Angeles, CA (US)
Assigned to Lemon Inc., Grand Cayman (KY)
Filed by Lemon Inc., Grand Cayman (KY)
Filed on Feb. 20, 2024, as Appl. No. 18/582,524.
Prior Publication US 2024/0248794 A1, Jul. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01)
CPC G06F 11/1004 (2013.01) [G06F 11/1068 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computing device for managing data integrity during a write operation, comprising:
a memory controller configured to:
receive a plurality of original data blocks, each original data block having an associated initial Cyclic Redundancy Check (CRC) value;
segment and recombine the received original data blocks into logic blocks;
calculate a new logic block CRC value for each logic block;
transmit the logic blocks with their respective new logic block CRC values to a storage device;
write the logic blocks to non-volatile memory of the storage device in the write operation;
calculate a combined CRC value for the logic blocks and a combined CRC value for the original data blocks;
compare the combined CRC values;
determine whether the combined CRC values match; and
responsive to determining that the combined CRC values match, generate and output a verification response verifying the integrity of the write operation.