US 12,481,546 B2
Self-healing low speed serial interface
Rajesh Bhaskar, Bangalore (IN); George Vergis, Portland, OR (US); Myron Loewen, Berthoud, CO (US); and Matthew A. Schnoor, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 15, 2022, as Appl. No. 17/671,903.
Prior Publication US 2022/0171669 A1, Jun. 2, 2022
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/14 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01)
CPC G06F 11/0757 (2013.01) [G06F 11/0772 (2013.01); G06F 11/141 (2013.01); G06F 13/1668 (2013.01); G06F 13/4291 (2013.01)] 14 Claims
OG exemplary drawing
 
7. A system comprising:
a two wire serial bus;
a controller coupled to the two wire serial bus; and
a target device coupled to the two wire serial bus, the target device including bus management circuitry to:
enable a watchdog timer in response to a first command received from the controller on the two wire serial bus,
reset the watchdog timer in response to a second command received from the controller prior to expiration of the watchdog timer,
initiate self-recovery if the watchdog timer expires prior to receiving the second command, and
send an in-band interrupt to the controller to indicate successful recovery.