US 12,481,504 B2
Apparatus and method for secure instruction set execution, emulation, monitoring, and prevention
Rajesh Poornachandran, Portland, OR (US); Vincent Zimmer, Issaquah, WA (US); and Prashant Dewan, Portland, OR (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2020, as Appl. No. 17/131,289.
Prior Publication US 2022/0197678 A1, Jun. 23, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 21/53 (2013.01)
CPC G06F 9/30181 (2013.01) [G06F 9/30145 (2013.01); G06F 9/3017 (2013.01); G06F 21/53 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
one or more registers to store rules specifying actions to be taken with respect to one or more instructions, a rule within the rules stored within the one or more registers to indicate one or more actions to be taken with respect to a matching instruction and an index to match an identifier of the matching instruction;
an evaluator to detect a request to execute a first instruction and to evaluate the first instruction based on the rules stored in the one or more registers, wherein upon a first rule corresponding to the first instruction specifying that execution of the first instruction is prohibited, the evaluator is to block execution of the first instruction, upon the first rule corresponding to the first instruction specifying that the execution of the first instruction is to be emulated, the evaluator is to cause the first instruction to be replaced with one or more emulated instructions, and upon no rule being found in the one or more registers applicable to the first instruction, the evaluator is to allow execution of the first instruction; and
an execution unit to execute the first instruction when the evaluator allows execution of the first instruction.