| CPC G06F 9/30036 (2013.01) [G06F 9/30038 (2023.08); G06F 9/3012 (2013.01); G06F 9/30145 (2013.01)] | 19 Claims |

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1. A processing apparatus comprising:
decode circuitry configured to decode instructions; and
processing circuitry configured to selectively apply vector processing operations specified by the instructions to input data vectors comprising a plurality of input data items at respective positions in the input data vectors,
wherein the decode circuitry is configured to, in response to a vector combining instruction specifying a plurality of source vector registers each comprising source data elements in a plurality of data element positions, one or more further source vector registers, and one or more destination registers, generate control signals to cause the processing circuitry to, for each data element position of the plurality of data element positions:
extract first source data elements from the data element position of each source vector register;
extract second source data elements from the one or more further source vector registers;
perform combining operations to generate a result data element, wherein the result data element is calculated by combining each element of the first source data elements and the second source data elements; and
store the result data element to the data element position of the one or more destination registers,
wherein the combining operations comprise:
source combining operations to generate intermediate data elements, each intermediate data element generated by combining a corresponding first source data element of the first source data elements with the second source data elements, and
intermediate combining operations to combine the intermediate data elements to generate the result data element.
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