US 12,481,465 B2
Host-preferred memory operation
Tony M. Brewer, Plano, TX (US); and Dean E. Walker, Allen, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 6, 2024, as Appl. No. 18/795,877.
Application 18/795,877 is a continuation of application No. 17/823,314, filed on Aug. 30, 2022, granted, now 12,079,516.
Prior Publication US 2024/0393983 A1, Nov. 28, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 9/38 (2018.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0607 (2013.01); G06F 9/3877 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory interface to control a memory device;
an external interface to receive a host request from a host for the memory device;
a near-memory accelerator to perform on operation an data represented in the memory device;
an internal interface to receive an internal request from the near-memory accelerator; and
a memory side cache with processing circuitry configured to:
maintain a host queue and an internal queue;
detect that the host request and the internal request both correspond to an element in a cache set of the memory side cache that is unavailable;
enqueue, based on detecting that the host request and the internal request both correspond to the element in the cache set that is unavailable, the host request in the host queue and the internal request in the internal queue; and
dequeue, based on the element of the cache set becoming available, the host request from the host queue before dequeuing the internal request from the internal queue for completion of the host request and the internal request.