US 12,481,459 B2
Devices and methods for deterministic interleaving of data from multiple hosts connected to a single port
Jonathan Hughes, Longmont, CO (US); Anilmurali Bhaviri, Longmont, CO (US); and Muhammad Mohsin Awan, Erie, CO (US)
Assigned to SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed by SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed on Dec. 14, 2023, as Appl. No. 18/540,605.
Prior Publication US 2025/0199719 A1, Jun. 19, 2025
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A device, comprising:
a port coupled to a bus, to which at least two hosts are communicatively coupled using an interposer;
memory circuitry; and
processing circuitry, coupled to the port and to the memory circuitry, the processing circuitry to:
receive a plurality of commands through the port, wherein the plurality of commands are from the at least two hosts using the interposer and wherein each command of the plurality of commands comprises a respective memory address and a respective port identification (ID);
segment each of the received commands into a plurality of segments, each segment being of a predetermined transfer size;
transmit each segment of each plurality of segments to a respective data structure instantiation corresponding to the port ID of the respective received command; and
perform data transfers for each respective segment of the plurality of segments by accessing the memory circuitry at each respective memory address associated with each respective segment.