US 12,481,454 B2
Apparatus, method and system to implement a dual VDM scheme on a three-dimensional memory architecture
Yasir Mohsin Husain, Folsom, CA (US); Xuming Zhao, Folsom, CA (US); Kevin E. Arendt, Orangevale, CA (US); and Sandeep Kumar Guliani, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 11, 2022, as Appl. No. 17/693,199.
Prior Publication US 2023/0289099 A1, Sep. 14, 2023
Int. Cl. G11C 16/10 (2006.01); G06F 3/06 (2006.01); G11C 13/00 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 13/0004 (2013.01); G11C 13/0038 (2013.01); G11C 13/004 (2013.01); G11C 13/0097 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus to be coupled to a memory array of a memory device, the apparatus including one or more processors to:
in response to a determination of a set command to be implemented on first memory cells of the memory array, control an execution of a set pre-read operation on the first memory cells by causing application, by a voltage source, of a first demarcation voltage VDM0 across each of the first memory cells during a set pre-read time period; and
in response to a determination of a reset command to implemented on second memory cells of the memory array, control an execution of a reset pre-read operation on the second memory cells by causing application, by the voltage source, of a second demarcation voltage VDM3 across each of the second memory cells during a reset pre-read time period, wherein the set pre-read time period and the reset pre-read time period do not overlap, the voltage source to supply a single voltage value at any given time.