US 12,481,453 B2
Unmapping a write buffer portion for access during a write to a memory device
Sai Naresh Gajapaka, Hyderabad (IN); Chintalapati Bharath Sai Varma, Hyderabad (IN); Santhosh Reddy Akavaram, Hyderabad (IN); Prakhar Srivastava, Lucknow (IN); and Vamsi Krishna Sambangi, Vizianagaram (IN)
Assigned to Qualcomm Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Aug. 2, 2023, as Appl. No. 18/364,277.
Prior Publication US 2025/0044982 A1, Feb. 6, 2025
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0608 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A memory device comprising:
a main memory;
a write buffer coupled to the main memory and to a bus interface; and
a memory controller configured to initiate a write buffer flush operation,
wherein the bus interface is coupled to the main memory and to the write buffer to receive a write command from a host during the write buffer flush operation, to send a last flushed address to the host, and to receive an unmap command from the host based on the last flushed address, and
wherein the memory controller is further configured, to suspend the write buffer flush operation in response to the write command, to send the last flushed address of the write buffer from the memory device to the host through the bus interface in response to suspension of the write buffer flush operation, wherein the last flushed address indicates a portion of the write buffer that has been flushed in the write buffer flush operation before the suspension of the write buffer operation, to process the write command after the suspension of the write buffer operation, and to unmap the portion of the write buffer in response to the unmap command using the last flushed address.