US 12,481,345 B2
Techniques for power management in compute circuits
Sreedhar Ravipalli, Cupertino, CA (US); Mahesh Kumashikar, Bangalore (IN); Md Altaf Hossain, Portland, OR (US); and Ankireddy Nalamalpu, Portland, OR (US)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2022, as Appl. No. 17/849,625.
Prior Publication US 2022/0334630 A1, Oct. 20, 2022
Int. Cl. G06F 1/32 (2019.01); G06F 1/3206 (2019.01); G06F 1/324 (2019.01)
CPC G06F 1/324 (2013.01) [G06F 1/3206 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit system comprising:
an accelerator circuit that generates a request in response to receiving packets of data, wherein the accelerator circuit generates an indication of a first low power state based on receiving a reduced number of the packets of data; and
a compute circuit that performs a processing operation for the accelerator circuit using the packets of data in response to receiving the request, wherein the compute circuit comprises a power management circuit that decreases a supply voltage in the compute circuit and decreases a frequency of a clock signal in the compute circuit in response to the indication of the first low power state from the accelerator circuit.