US 12,481,309 B2
System and methods of reducing wideband series resonant clock skew
Riadul Islam, Windsor Mill, MD (US); Dhandeep Challagundla, Baltimore, MD (US); and Ignatius Bezzam, Los Altos, CA (US)
Filed by University of Maryland Baltimore County, Baltimore, MD (US)
Filed on Apr. 5, 2024, as Appl. No. 18/627,479.
Claims priority of provisional application 63/494,380, filed on Apr. 5, 2023.
Prior Publication US 2024/0338053 A1, Oct. 10, 2024
Int. Cl. G06F 1/10 (2006.01); H03K 3/012 (2006.01); H03K 19/00 (2006.01)
CPC G06F 1/10 (2013.01) [H03K 3/012 (2013.01); H03K 19/0019 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A resonant clocking system for reducing wideband series resonant clock skew, comprising:
at least one Pulsed Series Resonance (PSR) driver that receives a boosted-amplitude pulsed signal VSR from a matching pulse generator;
at least one on-chip inductor connected with the at least one Pulsed Series Resonance (PSR) driver resonates with a capacitance of the resonant clocking system to generate a pulse signal RCLK;
at least one clock gater and at least one clock buffer that receive the pulse signal RCLK from the at least one PSR driver and propagate the pulse signal RCLK to clock pins of a resonant pulsed flip-flop,
wherein an inductance value of the at least one on-chip inductor is matched with a load capacitance of a corresponding branch capacitance using an inductor tuning technique to obtain equal frequency signals in all clock branches, thereby storing dissipated energy in a form of a magnetic field in the at least one on-chip inductor and reducing wideband series resonant clock skew.