US 12,480,990 B2
Technique for enabling on-die noise measurement during ate testing and IST
Bonita Bhaskaran, Santa Clara, CA (US); Nithin Valentine, Santa Clara, CA (US); Shantanu Sarangi, Santa Clara, CA (US); Mahmut Yilmaz, Santa Clara, CA (US); Suhas Satheesh, Santa Clara, CA (US); Charlie Hwang, Santa Clara, CA (US); Tezaswi Raja, Santa Clara, CA (US); Kevin Zhou, Santa Clara, CA (US); Sailendra Chadalavada, Santa Clara, CA (US); Kevin Ye, Santa Clara, CA (US); Seyed Nima Mozaffari Mojaveri, Santa Clara, CA (US); and Kerwin Fu, Santa Clara, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA CORPORATION, Santa Clara, CA (US)
Filed on Nov. 2, 2022, as Appl. No. 17/979,246.
Claims priority of provisional application 63/276,864, filed on Nov. 8, 2021.
Prior Publication US 2023/0146920 A1, May 11, 2023
Int. Cl. G01R 31/317 (2006.01); G01R 29/26 (2006.01); G01R 31/3177 (2006.01); G01R 31/319 (2006.01)
CPC G01R 31/31708 (2013.01) [G01R 29/26 (2013.01); G01R 31/31725 (2013.01); G01R 31/31727 (2013.01); G01R 31/3177 (2013.01); G01R 31/31905 (2013.01)] 45 Claims
OG exemplary drawing
 
1. A method for performing a scan test on a chip, the method comprising;
providing a first clock to a noise measurement (NMEAS) circuit of the chip while providing a second clock, which includes a portion that is slower than the first clock, to other logic of the chip during the scan test when the other logic is a device under test (DUT); and
measuring a voltage noise of the other logic using the NMEAS circuit during the scan test.