| CPC G01R 31/316 (2013.01) | 20 Claims |
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1. An integrated circuit comprising:
an analog delay circuit comprising a plurality of delay phases, a delay configuration input, and a signal input configured to receive a signal to be delayed, the plurality of delay phases comprising an initial delay phase and a final delay phase;
a sampler register comprising a signal input configured to receive the signal to be delayed, a plurality of test result outputs, and a plurality of delay inputs that are each coupled to a respective delay output of the plurality of delay phases, the sampler register being configured to
output a sample signal indicating a relationship between the signal to be delayed and at least the final delay phase of the plurality of delay phases; and
a test circuit comprising a delay configuration output coupled to the delay configuration input of the analog delay circuit, and a plurality of test result inputs coupled to the plurality of test result outputs of the sampler register, the test circuit being configured to
iterate through a plurality of selected delay values provided to the analog delay circuit at the delay configuration input to test the analog delay circuit, and
determine that the analog delay circuit passes the test in response to receiving the sample signal at the plurality of test result inputs by determining that the relationship matches a predetermined criterion.
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