US 12,480,987 B2
Dynamic voltage stress condition optimization method and dynamic voltage stress condition optimization system capable of performing block-based dynamic voltage stress wafer testing process
Yu-Lin Yang, Hsinchu (TW); Po-Chao Tsao, Hsinchu (TW); Yun-San Huang, Hsinchu (TW); Chia-Chun Sun, Hsinchu (TW); Chin-Wei Lin, Hsinchu (TW); Tung-Hsing Lee, Hsinchu (TW); Chih-Min Lin, Hsinchu (TW); and Chia-Yu Yang, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsin-Chu (TW)
Filed on Jan. 9, 2024, as Appl. No. 18/407,466.
Prior Publication US 2025/0224442 A1, Jul. 10, 2025
Int. Cl. G01R 31/28 (2006.01)
CPC G01R 31/2879 (2013.01) [G01R 31/287 (2013.01); G01R 31/2875 (2013.01); G01R 31/2894 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A dynamic voltage stress (DVS) condition optimization method comprising:
selecting a testing block from a plurality of testing blocks in a die of a wafer;
acquiring a plurality of testing block measurement temperatures of the testing block when the testing block is processed by a DVS testing flow;
acquiring a correlation table of the plurality of testing block measurement temperatures and a plurality of DVS block predict temperatures of the testing block;
configuring a tip burnt block temperature according to the testing block measurement temperatures;
determining a DVS block target temperature selected from the DVS block predict temperatures according to the correlation table and the tip burnt block temperature; and
generating a DVS block voltage for applying to the testing block in the die of the wafer according to the DVS block target temperature.