| CPC G01N 21/9501 (2013.01) [G06N 3/08 (2013.01); G06T 7/0004 (2013.01); G06T 2207/20081 (2013.01); G06T 2207/30148 (2013.01)] | 20 Claims |
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1. A computerized system of optimizing an inspection recipe for inspecting a semiconductor specimen, the system comprising a processing and memory circuitry (PMC) configured to:
obtain test data from a test performed on the semiconductor specimen after inspection thereof, the semiconductor specimen comprising one or more layers, each layer comprising structural features manufactured by a plurality of processing steps, the test data indicative of functional defectivity of the semiconductor specimen associated with at least one structural feature located on a suspected layer of the one or more layers;
retrieve inspection data of the suspected layer acquired during the inspection of the semiconductor specimen, the inspection data including a set of inspection images corresponding to at least a sampled set of the plurality of processing steps of the structural features of the suspected layer, and a set of defect maps corresponding to the set of inspection images and indicative of inspection defectivity with respect to the sampled set of the plurality of processing steps;
correlate the test data and the set of defect maps of the suspected layer to identify one or more structural features of the suspected layer with unmatched defectivity between the functional defectivity indicated by the test data and the inspection defectivity indicated by the set of defect maps;
prepare a training set, wherein, for each structural feature of the identified one or more of the structural features, at least part of the set of inspection images corresponding to the structural feature and ground truth data thereof, as indicated by the test data, are included in the training set; and
use the training set to train a machine learning (ML) model in the inspection recipe usable for inspection of a subsequent semiconductor specimen.
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