US 12,479,128 B2
Method for producing semiconductor wafers using a wire saw, wire saw, and semiconductor wafers made of monocrystalline silicon
Axel Beyer, Munich (DE); and Stefan Welsch, Polling (DE)
Assigned to Siltronic AG, Munich (DE)
Filed by SILTRONIC AG, Munich (DE)
Filed on Apr. 5, 2024, as Appl. No. 18/627,996.
Application 18/627,996 is a division of application No. 17/414,680, granted, now 12,083,705, previously published as PCT/EP2019/084802, filed on Dec. 12, 2019.
Claims priority of application No. 10 2018 221 922.2 (DE), filed on Dec. 17, 2018.
Prior Publication US 2024/0246260 A1, Jul. 25, 2024
Int. Cl. B28D 5/04 (2006.01); B24B 27/06 (2006.01); B28D 5/00 (2006.01); C30B 29/06 (2006.01); H01L 21/67 (2006.01); B23D 59/00 (2006.01); B28D 7/00 (2006.01); H01L 21/02 (2006.01); H01L 21/18 (2006.01)
CPC B28D 5/0064 (2013.01) [B24B 27/0633 (2013.01); B28D 5/0082 (2013.01); B28D 5/045 (2013.01); C30B 29/06 (2013.01); H01L 21/67092 (2013.01); H01L 21/67253 (2013.01); B23D 59/00 (2013.01); B28D 5/00 (2013.01); B28D 5/0058 (2013.01); B28D 5/007 (2013.01); B28D 5/04 (2013.01); B28D 7/00 (2013.01); H01L 21/0201 (2013.01); H01L 21/18 (2013.01); Y10T 428/31 (2015.01)] 7 Claims
OG exemplary drawing
 
1. A semiconductor wafer of monocrystalline silicon, having an upper side surface and a lower side surface, comprising
a warp of less than 1.2 μm;
a nanotopography of the upper side surface, expressed as THA25 10%, of less than 5 nm; and
a subsurface-referenced nanotopography of the upper side surface of less than 6 nm, expressed as a maximum peak-to-valley distance on a subsurface and referenced to subsurfaces with an area content of 25 mm×25 mm.