US 12,150,394 B2
Memory device structure for reducing thermal crosstalk
Ching Ju Yang, Hsinchu (TW); Huan-Chieh Chen, Taichung (TW); and Yao-Wen Chang, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 22, 2022, as Appl. No. 17/677,506.
Prior Publication US 2023/0270024 A1, Aug. 24, 2023
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/8616 (2023.02) [H10B 63/24 (2023.02); H10B 63/80 (2023.02); H10N 70/063 (2023.02); H10N 70/231 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a memory device, the method comprising:
depositing a data storage structure over a first conductive layer;
patterning the data storage structure to form data storage layers over the first conductive layer;
depositing a first spacer dielectric over the first conductive layer and on sidewalls of the data storage layers;
patterning the first spacer dielectric to form a first spacer layer, a first memory cell, and a second memory cell, wherein the first memory cell is spaced from the second memory cell;
patterning the first conductive layer to form a plurality of word lines below the first and second memory cells; and
forming a dielectric layer between the first and second memory cells such that an air gap is disposed within the dielectric layer, wherein the air gap is spaced laterally between the first memory cell and the second memory cell.