US 12,150,388 B2
Electroplating for vertical interconnections
Máté Jenei, Espoo (FI); Kok Wai Chan, Espoo (FI); Hasnain Ahmad, Espoo (FI); Manjunath Ramachandrappa Venkatesh, Espoo (FI); Wei Liu, Espoo (FI); Lily Yang, Espoo (FI); Tianyi Li, Espoo (FI); Jean-Luc Orgiazzi, Espoo (FI); Caspar Ockeloen-Korppi, Espoo (FI); Alessandro Landra, Espoo (FI); and Mario Palma, Espoo (FI)
Assigned to IQM Finland Oy, Espoo (FI)
Filed by IQM Finland Oy, Espoo (FI)
Filed on May 2, 2022, as Appl. No. 17/734,504.
Claims priority of application No. 20215519 (FI), filed on May 4, 2021.
Prior Publication US 2022/0359808 A1, Nov. 10, 2022
Int. Cl. H10N 60/01 (2023.01); H10N 60/81 (2023.01)
CPC H10N 60/01 (2023.02) [H10N 60/815 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first resist over a patterned wafer, the first resist defining one or more first openings through which one or more areas of the patterned wafer are exposed;
depositing an under bump metallization layer on the first resist and one or more exposed areas of the patterned wafer;
forming a second resist over the deposited under bump metallization layer, the second resist defining one or more second openings, each of the one or more second openings exposing an area of the under bump metallization layer within one of the one or more first openings;
depositing a flip chip bump within each of the one or more second openings in the second resist by electroplating; and
removing the first resist, the second resist, and areas of the under bump metallization layer that lie between the first resist and the second resist, wherein the patterned wafer includes one or more quantum processing unit components.