US 12,150,369 B2
Display panel, display device, test method and crack detection method
Linhong Han, Beijing (CN); Meng Zhang, Beijing (CN); Yi Zhang, Beijing (CN); Pengfei Yu, Beijing (CN); and Shikai Qin, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/275,230
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed May 19, 2020, PCT No. PCT/CN2020/091017
§ 371(c)(1), (2) Date Mar. 11, 2021,
PCT Pub. No. WO2021/232230, PCT Pub. Date Nov. 25, 2021.
Prior Publication US 2022/0115463 A1, Apr. 14, 2022
Int. Cl. H01L 27/32 (2006.01); G09G 3/00 (2006.01); H01L 51/00 (2006.01); H01L 51/56 (2006.01); H10K 59/121 (2023.01); H10K 59/122 (2023.01); H10K 59/124 (2023.01); H10K 59/131 (2023.01); H10K 59/88 (2023.01); H10K 71/00 (2023.01); H10K 71/70 (2023.01)
CPC H10K 59/88 (2023.02) [G09G 3/006 (2013.01); H10K 59/1216 (2023.02); H10K 59/122 (2023.02); H10K 59/124 (2023.02); H10K 59/131 (2023.02); H10K 71/00 (2023.02); H10K 71/70 (2023.02); G09G 2300/0809 (2013.01); G09G 2330/12 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a base substrate comprising a display area and a peripheral area on at least one side of the display area;
a plurality of sub-pixels on a side of the base substrate and in the display area;
a plurality of data signal lines in the display area and electrically connected to the plurality of sub- pixels;
a plurality of signal transmission lines in the peripheral area and electrically connected to the plurality of data signal lines;
a plurality of multiplexers in the peripheral area and on a side of the plurality of signal transmission lines away from the plurality of sub-pixels, at least one of the plurality of multiplexers being electrically connected to at least two signal transmission lines, wherein each of the plurality of multiplexers comprises a seventh transistor and an eighth transistor, wherein the seventh transistor and the eighth transistor share a first electrode serving as an input terminal of the each of the plurality of multiplexers, a second electrode of the seventh transistor is electrically connected to one of the at least two signal transmission lines, a control electrode of the seventh transistor is configured to receive a first selection signal, a second electrode of the eighth transistor is electrically connected to another of the at least two signal transmission lines, and a control electrode of the eighth transistor is configured to receive a second selection signal; and
a first test circuit in the peripheral area and one a side of the plurality of multiplexers away from the plurality of sub-pixels, the first test circuit comprising a plurality of test components, each test component of at least a portion of the plurality of test components being electrically connected to as least two of the plurality of multiplexers, and the each test component comprising a first test sub-circuit, a second test sub-circuit, and a third test sub-circuit, the second test sub-circuit being between the first test sub-circuit and the third test sub-circuit, and the first test sub-circuit being on a side of the second test sub-circuit away from the plurality of sub-pixels, wherein two adjacent multiplexers of the plurality of multiplexers are electrically connected to one of the plurality of test components through two connection wires,
wherein the plurality of multiplexers comprise a first multiplexer and a second multiplexer;
the first test sub-circuit comprises: a first transistor, a first electrode of the first transistor being configured to receive a first data signal, a second electrode of the first transistor being electrically connected to an input terminal of the first multiplexer, and a control electrode of the first transistor being configured to receive a first test switch signal; and a second transistor, a first electrode of the second transistor being configured to receive a second data signal, a second electrode of the second transistor being electrically connected to an input terminal of the second multiplexer, and a control electrode of the second transistor being configured to receive a second test switch signal;
the second test sub-circuit comprises: a third transistor, a first electrode of the third transistor being configured to receive a third data signal, a second electrode of the third transistor being electrically connected to the input terminal of the first multiplexer, and a control of the third transistor being configured to receive a third test switch signal; and a fourth transistor, a first electrode of the fourth transistor being configured to receive a fourth data signal, a second electrode of the fourth transistor being electrically connected to the input terminal of the first multiplexer, and a control electrode of the fourth transistor being configured to receive a fourth test switch signal; and
the third test sub-circuit comprises: a fifth transistor, a first electrode of the fifth transistor being configured to receive a fifth data signal, a second electrode of the fifth transistor being electrically connected to the input terminal of the second multiplexer, and a control electrode of the fifth transistor being configured to receive a fifth test switch signal; and a sixth transistor, a first electrode of the sixth transistor being configured to receive a sixth data signal, a second electrode of the sixth transistor being electrically connected to the input terminal of the second multiplexer, and a control electrode of the sixth transistor being configured to receive a sixth test switch signal.