| CPC H10B 61/20 (2023.02) [G11C 7/18 (2013.01); H10N 50/80 (2023.02)] | 8 Claims |

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1. A magnetoresistive random access memory (MRAM), comprising:
a first transistor and a second transistor on a substrate;
a source line coupled to a first source/drain region of the first transistor; and
a first metal interconnection coupled to a second source/drain region of the first transistor, wherein the first metal interconnection is extended to overlap the second transistor and an end of the first metal interconnection is coupled to a magnetic tunneling junction (MTJ).
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