US 12,150,313 B2
Magnetoresistive random access memory having a blocking layer on metal interconnection
Jia-Rong Wu, Kaohsiung (TW); I-Fan Chang, Tainan (TW); Rai-Min Huang, Taipei (TW); Ya-Huei Tsai, Tainan (TW); and Yu-Ping Wang, Hsinchu (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Nov. 2, 2023, as Appl. No. 18/500,994.
Application 18/500,994 is a continuation of application No. 17/888,451, filed on Aug. 15, 2022, granted, now 11,849,592.
Application 17/888,451 is a continuation of application No. 16/857,152, filed on Apr. 23, 2020, granted, now 11,456,331, issued on Sep. 27, 2022.
Claims priority of application No. 202010235266.X (CN), filed on Mar. 30, 2020.
Prior Publication US 2024/0074209 A1, Feb. 29, 2024
Int. Cl. H10B 61/00 (2023.01); G11C 11/16 (2006.01); H01F 10/32 (2006.01); H01F 41/34 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01)
CPC H10B 61/00 (2023.02) [G11C 11/161 (2013.01); H01F 10/3254 (2013.01); H01F 41/34 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H10N 50/01 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate having a logic region and a magnetoresistive random access memory (MRAM) region;
more than one MTJs on the MRAM region;
a metal interconnection on the more than one MTJs; and
a blocking layer on the metal interconnection, wherein the blocking layer comprises a stripe pattern according to a top view and the stripe pattern overlaps the more than one MTJs.