CPC H10B 51/30 (2023.02) [G11C 11/223 (2013.01); H01L 27/1211 (2013.01)] | 20 Claims |
1. A ferroelectric memory device, comprising:
a pair of source/drain regions disposed in a substrate;
a gate dielectric disposed over the substrate and between the pair of source/drain regions;
a gate electrode disposed on the gate dielectric;
a polarization switching structure disposed over the gate electrode with a lateral dimension smaller than that of the gate electrode; and
a pair of sidewall spacers disposed over the substrate and along opposite sidewalls of the gate electrode and the polarization switching structure.
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