| CPC H10B 51/30 (2023.02) [H01L 23/5226 (2013.01); H10B 12/31 (2023.02); H10B 53/40 (2023.02)] | 20 Claims |
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1. A semiconductor chip, comprising:
a semiconductor substrate comprising first transistors;
an interconnect structure disposed over the semiconductor substrate and electrically connected to the first transistors, the interconnect structure comprising stacked interlayer dielectric layers, interconnect wirings, and second transistors embedded in the stacked interlayer dielectric layers; and
memory devices embedded in the stacked interlayer dielectric layers and electrically connected to the second transistors, wherein the second transistors comprise a first group of second transistors disposed at a first level height and a second group of second transistors disposed at a second level height different from the first level height, and wherein the memory devices comprise a first group of memory devices disposed at a third level height and a second group of memory devices disposed at a fourth level height different from the third level height,
wherein in the interconnect structure, layers of the memory devices and layers of second transistors are disposed correspondingly, and the third level height is between the first level height and the second level height, and the fourth level height is above the second level height,
wherein the interconnect wirings comprise through vias, and two of the through vias are respectively disposed next to two opposite sides of each of the memory devices and penetrate through two vertical adjacent stacked interlayer dielectric layers to electrically connect to a corresponding one of the second transistors.
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