US 12,150,304 B2
Methods for forming multi-layer vertical NOR-type memory string arrays
Scott Brad Herner, Portland, OR (US); Wu-Yi Henry Chien, San Jose, CA (US); Jie Zhou, San Jose, CA (US); and Eli Harari, Saratoga, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed on Oct. 31, 2023, as Appl. No. 18/499,091.
Application 18/499,091 is a division of application No. 17/669,024, filed on Feb. 10, 2022, granted, now 11,844,217.
Application 17/669,024 is a division of application No. 16/707,920, filed on Dec. 9, 2019, granted, now 11,282,855, issued on Mar. 22, 2022.
Claims priority of provisional application 62/777,000, filed on Dec. 7, 2018.
Prior Publication US 2024/0099003 A1, Mar. 21, 2024
Int. Cl. H10B 43/27 (2023.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01)
CPC H10B 43/27 (2023.02) [H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 21/31116 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method for high aspect-ratio etching, comprising:
preparing above a planar surface of a semiconductor substrate a plurality of multi-layers, stacked one on top of another, along a first direction that is substantially orthogonal to the planar surface, wherein each multi-layer comprises a first layer and a second layer, the first layer being of a first dielectric material and the second layer being of a first material;
using a first mask, defining and etching a plurality of shafts, each shaft extending over substantially an entire length of the multi-layers along the first direction;
filling the shafts with a second dielectric material to form a plurality of pillars;
using a second mask, etching a plurality of trenches in the multi-layers without substantially removing the second dielectric material from the pillars, each of the trenches extending along a second direction substantially parallel to the surface of the semiconductor substrate;
replacing the first material with a conductive material;
selectively etching first portions of the filled trenches to provide a second plurality of shafts that each extend along the first direction;
depositing a charge storage material conformally in each of the second plurality of shafts;
depositing a semiconductor layer of a first conductivity conformally over the charge storage material; and
filling each of the second plurality of shafts with a third dielectric material.