US 12,150,296 B2
Method for manufacturing semiconductor bit line contact region with different doped impurity concentrations
Xun Yan, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jun. 7, 2022, as Appl. No. 17/805,738.
Application 17/805,738 is a continuation of application No. PCT/CN2022/071263, filed on Jan. 11, 2022.
Claims priority of application No. 202111192543.4 (CN), filed on Oct. 13, 2021.
Prior Publication US 2023/0114038 A1, Apr. 13, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/482 (2023.02) [H10B 12/03 (2023.02); H10B 12/09 (2023.02); H10B 12/485 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor structure, comprising:
providing a substrate, wherein a plurality of bit line contact regions arranged at intervals are provided in the substrate;
forming a first conductive layer in each of the bit line contact regions, wherein the first conductive layer defines a contact hole in each of the bit line contact regions; and
forming a second conductive layer in each of the contact holes, wherein the second conductive layer and the first conductive layer form a conductive layer, and a concentration of doped impurities in the second conductive layer is higher than a concentration of doped impurities in the first conductive layer.