US 12,150,294 B2
Method for manufacturing semiconductor structure and same
Zhongming Liu, Hefei (CN); Shijie Bai, Hefei (CN); and Longyang Chen, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Dec. 8, 2021, as Appl. No. 17/545,213.
Application 17/545,213 is a continuation of application No. PCT/CN2021/120250, filed on Sep. 24, 2021.
Claims priority of application No. 202110226832.5 (CN), filed on Mar. 1, 2021.
Prior Publication US 2022/0278107 A1, Sep. 1, 2022
Int. Cl. H10B 12/00 (2023.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H10B 12/482 (2023.02) [H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H10B 12/315 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
providing a base, a plurality of bit lines extending in a first direction and a groove located between two adjacent ones of the bit lines being provided on the base;
forming an initial contact layer and an initial protection layer filling the groove, the initial contact layer being in contact with the base, the initial protection layer being located on the initial contact layer;
performing a patterning treatment to the initial contact layer and the initial protection layer, so as to form a plurality of contact layers that are discrete from each other and a plurality of protection layers that are discrete from each other;
forming a dielectric layer between two adjacent ones of the contact layers, the dielectric layer being further located between two adjacent ones of the protection layers, a material of the dielectric layer being different from a material of the protection layers; and
after forming the dielectric layer, removing the protection layers.