US 12,150,237 B2
Method and procedure for miniaturing a multi-layer PCB
Robert Migliorino, Wayne, NJ (US); Michael Mirabella, Lanoka Harbor, NJ (US); and Clint Smith, Warwick, NY (US)
Assigned to VEEA Inc., New York, NY (US)
Filed by Veea Inc., New York, NY (US)
Filed on Nov. 7, 2022, as Appl. No. 18/053,264.
Application 18/053,264 is a continuation in part of application No. 17/313,073, filed on May 6, 2021, granted, now 11,523,502.
Claims priority of provisional application 63/020,745, filed on May 6, 2020.
Prior Publication US 2023/0087792 A1, Mar. 23, 2023
Int. Cl. H05K 1/02 (2006.01); H05K 1/11 (2006.01)
CPC H05K 1/0206 (2013.01) [H05K 1/0218 (2013.01); H05K 1/115 (2013.01); H05K 2201/066 (2013.01); H05K 2201/09609 (2013.01); H05K 2201/09854 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multi-layer printed circuit board (PCB), comprising:
a plurality of layers including:
a pair of signal layers,
a plurality of prepreg substrate layers disposed between the pair of signal layers,
a plurality of ground plane layers, wherein each of the plurality of ground plane layers abuts one of the plurality of prepreg substrate layers,
a plurality of inner signal layers, wherein each of the plurality of the inner signal layers abuts one of the plurality of prepreg substrate layers, and
a core substrate layer disposed between the pair of signal layers, wherein two of the plurality of inner signal layers abut opposed sides of the core substrate layer;
one or more vertical interconnect accesses (VIAs) extending through at least some of the plurality of layers, wherein each of the one or more VIAs is formed by aligned apertures through adjoining ones of at least one of the plurality of prepreg substrate layers, at least one of the plurality of ground plane layers, and at least one of the plurality of inner signal layers; and
a vertical interconnect access (VIA) bridge formed of conductive material and coupled to at least one of the one or more VIAs to convey heat from the at least one of the one or more VIAs to a heat sink.