CPC H04W 28/0278 (2013.01) [H04W 72/21 (2023.01); H04W 72/23 (2023.01); H04B 7/15528 (2013.01)] | 17 Claims |
1. An apparatus for a first node, comprising at least one processor and a non-transitory memory storage coupled to the at least one processor and storing programming instructions for execution by the at least one processor, wherein the programming instructions instruct the at least one processor to perform operations comprising:
determining first information, wherein the first information indicates a downlink buffer status of a first bearer between the first node and a second node, and the first bearer is an ingress radio link control (RLC) channel, and the first information comprises a logical channel identifier (LCID) that identifies the ingress RLC channel; and
sending the first information to the second node, wherein
the first node is a relay node in a wireless relay communications system, and the second node is a parent node of the first node.
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