US 12,149,853 B2
Photoelectric conversion device, electronic device, and substrate
Hideo Kobayashi, Tokyo (JP)
Assigned to Canon Kabushiki Kaisha, Tokyo (JP)
Filed by CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed on Nov. 1, 2023, as Appl. No. 18/499,545.
Application 18/499,545 is a continuation of application No. 17/588,484, filed on Jan. 31, 2022, granted, now 11,843,893.
Claims priority of application No. 2021-016892 (JP), filed on Feb. 4, 2021.
Prior Publication US 2024/0064439 A1, Feb. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 25/772 (2023.01); H04N 25/616 (2023.01)
CPC H04N 25/772 (2023.01) [H04N 25/616 (2023.01)] 19 Claims
OG exemplary drawing
 
1. A photoelectric conversion device comprising:
a pixel portion in which a plurality of pixels, each including a photoelectric conversion element, are arranged in a matrix;
a sample-and-hold unit configured to sample a signal generated in the photoelectric conversion element via a vertical signal line from the pixel portion and hold the signal; and
a conversion unit configured to perform an analog-to-digital conversion on a signal outputted from the sample-and-hold unit,
wherein in the sample-and-hold unit, a first sample-and-hold circuit that samples a signal for when the photoelectric conversion element is reset and a second sample-and-hold circuit that samples a signal for when a photoelectric conversion operation is performed in the photoelectric conversion element are connected to one vertical signal line,
wherein the pixel portion is arranged on a first substrate,
wherein a part of a group, the group being configured by the sample-and-hold unit and the conversion unit, and a first current source configured to provide a current to the sample and hold unit, are arranged on a second substrate,
wherein another part of the group and a second current source configured to provide a current to the conversion unit are arranged on a third substrate,
wherein in the sample-and-hold unit, a third sample-and-hold circuit is connected to a vertical signal line different from the one vertical signal line, and
wherein a distance between a capacitive element included in the first sample-and-hold circuit and a capacitive element included in the second sample-and-hold circuit is shorter than a distance between the capacitive element included in the first sample-and-hold circuit and a capacitive element included in the third sample-and-hold circuit.