US 12,149,848 B2
Photoelectric conversion apparatus, photoelectric conversion system, moving body, and semiconductor substrate
Hideo Kobayashi, Tokyo (JP); and Takanori Suzuki, Tokyo (JP)
Assigned to Canon Kabushiki Kaisha, Tokyo (JP)
Filed by CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed on Dec. 14, 2021, as Appl. No. 17/550,692.
Claims priority of application No. 2020-215239 (JP), filed on Dec. 24, 2020.
Prior Publication US 2022/0208810 A1, Jun. 30, 2022
Int. Cl. H04N 25/75 (2023.01); H04N 25/766 (2023.01); H04N 25/77 (2023.01); H04N 25/79 (2023.01)
CPC H04N 25/766 (2023.01) [H04N 25/75 (2023.01); H04N 25/77 (2023.01); H04N 25/79 (2023.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a pixel array in which a plurality of pixels including a first pixel, a second pixel, a third pixel, and a fifth pixel is arranged,
wherein in a top plan view of the pixel array, the fifth pixel, the first pixel, the second pixel, and the third pixel are arranged along a positive direction of a first direction in order,
wherein the first pixel is connected to a first line,
wherein the second pixel is connected to a second line,
wherein the third pixel is connected to a third line,
wherein the fifth pixel is connected to a fifth line,
wherein the first line is connected to a first processing circuit,
wherein the second line is connected to a second processing circuit,
wherein the third line is connected to a third processing circuit,
wherein the fifth line is connected to a fifth processing circuit,
wherein the first processing circuit, the second processing circuit, the third processing circuit and the fifth processing circuit are arranged along the first direction, and the first processing circuit is located between the second processing circuit and the third processing circuit, and the second processing circuit is located between the first processing circuit and the fifth processing circuit,
wherein a first processing circuit group includes the first processing circuit and the third processing circuit,
wherein a second processing circuit group includes the second processing circuit and the fifth processing circuit,
wherein the first processing circuit group performs first calculation processing of generating a first signal by using a pixel signal read from the first line and a pixel signal read from the third line, and
wherein the second processing circuit group performs second calculation processing of generating a second signal by using a pixel signal read from the second line and a pixel signal read from the fifth line.