US 12,149,643 B2
Device signature based on trim and redundancy information
Katherine H. Chiang, New Taipei (TW); and Shih-Lien Linus Lu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 21, 2023, as Appl. No. 18/515,613.
Application 18/515,613 is a continuation of application No. 17/174,948, filed on Feb. 12, 2021.
Prior Publication US 2024/0089126 A1, Mar. 14, 2024
Int. Cl. G06F 21/00 (2013.01); H04L 9/06 (2006.01); H04L 9/32 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01)
CPC H04L 9/3278 (2013.01) [H04L 9/0643 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
one or more circuits;
one or more interconnect routings;
a trim circuit configured to adjust one or more operational characteristics of the one or more circuits based on trim information comprising one or more tuning parameters of the adjusted one or more operational characteristics;
a redundancy circuit configured to replace one or more defective portions of the one or more interconnect routings based on redundancy information comprising an address mapping of the replaced one or more defective portions; and
a processor configured to:
extract bits from the trim and redundancy information;
perform a hashing function on the extracted bits to generate hashed bits; and
in response to statistical properties of the hashed bits meeting one or more criteria, output the hashed bits.